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ECARX debuts EXP01 processor at RISC-V Summit Europe 2025
On May 16, ECARX Holdings Inc. announced the debut of its EXP01 processor built on the RISC-V architecture at the RISC-V Summit Europe 2025, which was held from May 12-15, 2025, in Paris. ECARX showcased EXP01, its first processor design built on the 32-bit RISC-V ISA. EXP01 uses a dual-core safety architecture in wh....
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